The demand for high performance mixed-signal integrated circuits has continuously necessitated both the miniaturization of devices and higher operating frequencies. However, the performance of the interconnections between devices has progressed at a slower pace. As a result, interconnect has become one of the most severe bottlenecks impacting the realization of nanoscale integrated circuits. Increasing interconnect noise, delay, power, thermal effects and process variations can severely impact circuit performance and reliability. Several new design strategies such as network-on-chip (NoC) and 3-D integrated circuits have emerged to facilitate more efficient on-chip communication. Understanding how to effectively utilize these new design paradigms/architectures to realize high performance interconnect solutions is crucial. Our research is focused in the following areas:

• Reliability Analysis of Network-on-Chip (NoC) Interconnects
• Design Methodologies for Mitigating Thermal Effects and Enabling Low Power Circuit Operation
• RLC Modeling of Interconnect for High Performance System-On-Chip Applications

Network-on-Chip (NoC) has emerged as a vital technology to establish a controlled communication mechanism between system-level blocks to provide greater performance and reliability. NoC architectures consist of an ensemble of links that work as shared resources by time-multiplexing to facilitate more robust global on-chip communication. NoC has emerged as a viable alternative to traditional point-to-point interconnect for conventional and 3-D integrated circuit designs in current and future nanoscale integrated circuits. However, with CMOS technology scaling, hardware defects have increased in both the devices and interconnects, resulting significant yield loss. In an NoC context, there will be a probability that a particular link will fail due to process variation, which must be considered for the optimal physical design for NoCs. Our current research involves the development of models for the probability of link failure caused by delay uncertainty due to process variation and its impact on the performance and reliability of NoC architectures.

On-chip temperature gradients have become an important factor for the performance and reliability of nanoscale integrated circuits. On-chip temperature gradients arise from the structural difference and diversity of computational activities across the chip. In modern processors, intra-chip temperature differences can be as high as 50oC, which can be detrimental to the performance and reliability of the both devices and interconnect. Our current research focuses on the modeling and analysis of on-chip thermal effects in both 2-D and 3-D integrated circuits to determine the performance of the design under thermal gradients. We are also developing intelligent design solutions for mitigating thermal effects. Our recent work involves the design of thermally adaptive clock buffers that dynamically sense the surrounding temperature and adjusts the buffer drive strength to counteract the temperature-dependent performance degradation.

With the aggressive scaling of process technology into the nanoscale regime, interconnect is greatly impacting the performance and reliability of digital circuits. The accurate and efficient RLC modeling of the on-chip interconnect is crucial for both timing and noise estimation. Due to the computational complexity associated with traditional field solver-based extraction solutions, analytical models are essential for incorporating interconnect parasitics during the initial phases of the design process. We have developed an accurate analytical inductance model for generic layout structures that can be utilized for interconnect synthesis and optimization. Our analytical inductance modeling technique performs accurately when compared with simulations using numerical field solvers with up to three orders of magnitude speedup. Accurate and fast inductance modeling is key element in the development of signaling techniques that will facilitate the realization of high performance, robust and low noise circuits. We are currently investigating novel signaling solutions that can successfully mitigate the impact of technology scaling on SoC designs.