RAND

The growing demand for integrated wireless and other mixed-signal system-on-chip (SoC) designs has spurred the need for innovative design automation techniques to improve performance, reliability and time-to-market. To successfully realize increasingly complex mixed-signal integrated circuits, robust design automation techniques in the analog domain must be developed to rapidly generate reliable systems that meet design requirements. By leveraging the power of design automation, analog and mixed-signal integrated circuits will deliver greater functionality, increased performance and improved reliability. Our research is focused in the following areas:

• Synthesizing Fully Integrated Low Noise Amplifiers for On-Chip Wireless Applications
• Modeling and Automated Design of Integrated Spiral Inductors
• Integrated Hierarchical Synthesis for Baseband Analog Applications

Given the increasing demand for wideband and multi-band reconfigurable wireless systems implemented in mixed-signal integrated circuits, the automated design and optimization of fully integrated CMOS Low Noise Amplifiers (LNA) is vital for meeting power and performance requirements while substantially reducing time-to-market and cost. Successful LNA designs will efficiently balance critical figures of merit including noise figure, gain, power consumption, and input and output impedance matching (Figure 1) at a specific set of frequencies. In addition to these important design considerations, fully integrated LNA designs must also consider the impact of circuit element sizing and the parasitic effects that are inherently present in the SoC environment. LNA synthesis methodologies that account for these important design constraints will deliver designs with greater functionality, increased performance and improved reliability.

We have developed an automated design methodology for fully integrated LNAs that leverages the efficiency of the analytical modeling techniques and the flexibility of numerical optimization methods. The developed automated design method includes the following aspects/features:

• Created an accurate analytical LNA models for use in the automated LNA synthesis process
  • Can model various input and output network configurations and transistor short channel effects
  • Utilizes our spiral inductor synthesis techniques for inductor characterization and optimization in LNA impedance matching networks
  • Analytical LNA performance models validated using circuit-level simulation
  • Generalized LNA impedance matching networks enable variability-aware wideband and multi-band functionality
• Developed an LNA optimization methodology that numerically determines passive component values and transistor sizes to maximize performance
  • Simultaneously optimizes noise figure, gain, power, impedance matching, linearity and area
  • Concurrently considers both device and passive component values
  • Optimizes LNA performance over the entire wideband / multi-band frequency range
  • Provides flexibility to probe LNA performance trade-offs
  • Guarantees LNA suitability for SoC integration by constraining passive component values
• Modeling and automated design methodologies can be utilized to synthesize single-band, wideband and multi-band LNAs
• Results demonstrate efficacy of the developed modeling and automated design methods
  • Automated design method provides orders of magnitude reduction in inductance and resistance compared to LNAs produced with traditional equation-based design techniques (Figure 2)
  • Used method to numerically explore design trade-offs between figures of merit such as noise figure and power consumption (Figure 3)
  • Can generate wideband (Figure 4) and multi-band (Figure 5) LNAs with user-specified frequency ranges and design specifications
• Our LNA synthesis methodology generates wideband and multi-band designs with component values that can be integrated into the SoC environment while meeting user-specified performance requirements

Accurate and efficient modeling and optimization of integrated RF spiral inductors continue to be an important challenge on the path to the automated design of analog and mixed-signal systems. Spiral inductors suffer complex loss mechanisms in the metal and substrate, and consume large chip area, making them difficult to model and expensive to implement. The large inductor design space necessitates efficient optimization methodologies that facilitate the automated synthesis of numerous analog circuits such as low noise amplifiers (LNA), voltage controlled oscillators (VCO) and RF filters. Consequently, accurate design and optimization of spiral inductors are critical to a successful and cost-effective realization of analog circuits in fully integrated mixed-signal and RF systems.

We created a modeling and automated design method for on-chip inductors in mixed-signal integrated circuits. The developed automated design method for integrated spiral inductors includes the following aspects/features:

• Created an accurate analytical model for integrated spiral inductors
  • Captures a plethora of loss mechanisms in the inductor’s conductors and the substrate (Figure 6)
  • Analytical model is accurate when compared with field solvers and fabricated spiral inductors (Figure 6)
  • Model provides up to 5 orders of magnitude speedup over field solver-based solutions (Figure 6)
• Developed an automated design methodology that optimizes the inductor’s geometry
  • Considers the inductor’s quality factor and inductance value at a particular set of operating frequencies as well as the inductor’s self-resonant frequency and area
  • Generates inductor designs with substantially larger quality factors that those realized using manual design techniques with an area reduction of 50% or more
  • Pareto optimization facilitates efficient inductor utilization in higher level circuits
• The synthesis methodology enables the efficient analysis and exploitation of key design parameters to generate high performance integrated inductors designs

Figure 6: The developed automated design method captures/minimizes the plethora of loss mechanisms that impact the performance of integrated spiral inductors. The method’s results are accurate compared to field solver simulations and fabricated inductors while achieving up to 5 orders of magnitude in computational speedup

The characterization of deep sub-micron (DSM) effects such as induced barrier lowering, reverse short channel effect, mobility degradation, drain-source resistance and substrate leakage has increased the complexity of the device models dramatically. DSM effects particularly impact highly complex circuits such as PLLs and sigma delta analog to digital converters (Σ∆-ADC). More complex device models and simulators are essential for capturing DSM effects. Therefore, design time and complexity are increasing as the technology scales, which reduces overall productivity and cost. Due to extensive device simulation time and number of design parameters, conventional design approaches do not guarantee the achievement of the optimal design since they do not poses the speed to search the entire design space. To manage the complexity associated with mixed-signal designs, we are developing an Integrated Hierarchical Mixed-Signal Synthesis framework for analog designs in SoC technology. We are currently utilizing our methodology to target the design automation of sigma delta analog to digital converters (ΣΔ-ADC).

In our preliminarily work, we are developing behavioral models to characterize the various building blocks of a Gm-C based continuous-time (CT) Σ∆-ADC. We will utilize our behavioral models to build the hierarchical mixed-signal synthesis flow for the CTΣ∆-ADC, which we will expand to other A/D architectures. Our behavioral models describe the Gm-C integrators, Gm-C resonators, comparator and feedback DAC. Our preliminary models accurately capture the various non-idealities in the CTΣ∆-ADC with an error less than 3%. The complete behavioral simulation of the modulator using our modeling approach is less than 2 minutes when compared to a 33 hours of simulation using the circuit level descriptions. In addition to our modeling techniques for the integrator and modulator, our models for the comparator block of the A/D accurately captures excess loop delay, meta-stability, clock jitter, hysteresis, DC offset and feedback pulse shape. In the near term, by combining systematic modeling and optimization approaches with specific information pertaining to individual circuits and systems, we will be able to manage the complexity that has so far limited the realization of CTΣ∆-ADC synthesis. In the long-term, our synthesis methodology will enable greater functionality, increased performance and improved reliability with substantially lower cost, which will streamline the development of high performance ADCs.