RAND

The modeling, design, and implementation of on-chip interconnect continues to be a fundamental roadblock to realizing high-performance integrated systems. As wire width decreases, traditional copper interconnect in high performance VLSI systems will suffer significant increases in resistivity due to surface roughness and grain boundary scattering. The increase in resistance will lead to delay and electromigration problems, which will limit both performance and reliability. Carbon nanotubes (CNT) have been proposed as a possible replacement for on-chip copper interconnect due to their large conductivity and current carrying capabilities. While CNTs have desirable material properties, individual nanotubes suffer from a large intrinsic resistance that is not dependent on the length of the nanotube. To alleviate the intrinsic resistance problem, bundles or ropes of CNTs in parallel (Figure 1) have been proposed and physically demonstrated as a possible interconnect medium for local and global interconnect as well as vias connecting metal layers.

To provide a comprehensive analysis of the performance and reliability of CNT bundles for both local and global interconnect in future VLSI applications, we are developing modeling and design solutions for nanotube-based interconnect. Leveraging our CNT circuit model, we are examining the performance and reliability of nanotube bundles for interconnect applications in future nano-architectures. Our research is focused in the following areas:

• RLC Modeling of Carbon Nanotube Bundle Interconnect
• Predicting the Performance of Carbon Nanotube-Based Interconnect Solutions
• Future FPGA Design with Nanotube-Based Interconnect

To facilitate the development of nanotube-based interconnect solutions, we have created modeling techniques for nanotube-based structures including individual and bundled single-walled and multi-walled carbon nanotubes (Figure 1). The models capture the effective resistance, capacitance, and inductance of CNTs resulting from both electromagnetic and quantum effects while accurately incorporating recent experimental and theoretical results. The developed modeling techniques include the following aspects/features:

• Developed an RLC circuit model for CNT bundles (Figure 1)
  • Based on a Luttinger liquid theory model for 1-D conduction channels in CNTs
  • Captures physical effects including the probability distribution of metallic/semiconducting nanotubes, acoustic and optical phonon scattering, and contact barriers formed at CNT-metal interfaces
  • Closely matches electrical characterization results from experimental studies
• Created closed-form formulations for each RLC circuit element
  • Diameter-dependent models for the ohmic and contact resistance of CNTs
  • Scalable magnetic and kinetic inductance modeling solutions for CNT bundles with a large number of individual nanotubes including high frequency current redistribution
  • Electrostatic and quantum capacitance models for complex CNT geometries in the integrated circuit environment
• Identified and characterized potential sources of process variations for CNT-based interconnect solutions (Figure 2)
• Models provide a framework to evaluate the performance and reliability of future CNT-based interconnect solutions

Figure 1: Carbon nanotube bundle interconnect and its equivalent circuit model

Figure 2: Sources of process variation captured using the CNT bundle interconnect model

Leveraging our equivalent RLC circuit model, we have investigated the performance and reliability of nanotube-based interconnect solutions for local, intermediate, and global interconnect applications for various geometries and process parameters. We examined the performance implications of magnetic and kinetic inductance for nanotube-based interconnect solutions. Given the manufacturing challenges associated with future nanotube-based interconnect, we also investigate the impact of the process variations associated with nanotube-based interconnect and compare these sources of variation to those in scaled copper wires to evaluate the reliability of future nanotube-based interconnect solutions. Our investigation of the performance and reliability of CNT-based interconnect solutions has yielded the following results/conclusions:

• CNT bundles can provide significantly lower resistivity than standard copper wires (Figure 3)
  • Smaller individual CNT diameters lead to lower resistivity
  • Must capture diameter dependent CNT resistance for accurate characterization
• Lower CNT resistivity can lead to large delay improvements over standard copper interconnect in future process technologies (Figure 4)
  • Global wires receive the most benefit from the smaller CNT resistance
  • Fixed nanotube contact resistance increases delay for short wires
  • Magnetic inductance dominates kinetic inductance in terms of delay impact
  • Metallic nanotube probability can have a large effect on the performance CNT-based interconnect
• Process variations for CNT bundles will be significant and must be considered in future nanotube-based interconnect solutions
• CNT bundles are a promising future VLSI interconnect solution

Figure 3: Effective ohmic resistivity versus individual nanotube diameter for dense and sparse nanotube bundles modeled with and without the developed diameter-dependent resistance formulation

Figure 4: Predicted delay improvement provided by single-walled CNT bundle-based interconnect versus the probability that a given nanotube is metallic and the length of the bundle

Given the increasing demand for Field Programmable Gate Arrays (FPGAs) as hardware platforms in reconfigurable applications, the development of FPGAs with greater performance is crucial. While the reconfigurable nature of FPGAs makes them an attractive hardware solution, they can suffer from large overheads (area, delay, and power) because of their programmable interconnect fabric. Given the long-term scaling problems associated with traditional copper wires, alternative interconnect technologies and their architectural implications for FPGAs in future process technologies must be explored. To improve the performance of FPGAs in future process technologies, we propose utilizing nanotube-based interconnect solutions in the FPGA interconnect fabric (Figure 5). We examined several architectural features of an FPGA including different segment lengths and switch populations in the interconnect fabric to optimize the performance of CNT-FPGA architectures. We predict that FPGAs that utilize nanotube-based interconnect can achieve a significant improvement in average area-delay product when using an optimized FPGA architecture over FPGAs implemented with scaled copper interconnect in future process technologies.